1. Technical Field
The present invention relates to semiconductor fabrication, and more particularly to device encapsulation to protect back end of line features.
2. Description of the Related Art
Processing of a semiconductor wafer is divided into different regimes or groups of steps. These regimes are commonly referred to as front-end-of-the-line (FEOL); middle-of-the-line (MOL) and back-end-of-the-line (BEOL). FEOL generally refers to the regime for forming devices on or in a semiconductor wafer, e.g., forming diffusion regions, active areas, etc. MOL is the regime where conductive structures are connected to the FEOL devices. BEOL is the regime for final wafer processing where an active region is connected to outside circuitry. BEOL materials are often porous and have poor resistance to wet etchant. Therefore, wet etching is usually never used in BEOL processing. In addition, thermal budget is strictly limited at BEOL to prevent damage to already-fabricated devices and the like. Once outer dielectric and polymer chip encapsulation layers are defined, the stack is referred to as a far back end of the line (FBEOL) stack. FBEOL is a sub-regime of BEOL.